1. Field of the Invention
This invention relates to semiconductor memories and more particularly to flash memories and the method of manufacture thereof.
2. Description of Related Art
FIG. 2 shows a fragmentary sectional view of a prior art flash memory cell 4. Memory cell 4 includes a P- substrate 5 with an array of N+ buried bitline regions 9 therein forming buried bitlines BL1, BL2, BL3 and BL4 which extend back into the page. The buried bitlines 9 are formed in the surface of substrate 5. Above the substrate and the buried bitlines 9 is a thin tunnel oxide layer 6 having a thickness less than 100 .ANG.. Polysilicon 1 floating gates FG1, FG2 and FG3 lie above the thin tunnel oxide layer 6. A dielectric layer 7 covers the floating gates FG1, FG2 and FG3. Above the dielectric layer 7 is formed a polysilicon 2 control gate (wordline) layer 8 extending transversely across the floating gates FG1, FG2 and FG3. The control gate (wordline) layer 8 overlies the floating gates FG1, FG2 and FG3 extending across the cell 4. The program and erase operations are performed through a thin tunnel oxide layer 6. A program operation is performed by pulling an electron from a buried N+ bitline 9 through the tunnel oxide layer 6 to a floating gate FG1. An erase operation is performed by pulling an electron from the floating gate FG1 through the tunnel oxide layer 6 into a buried bitline 9.
One problem with the device of FIG. 2 is the limited efficiency of the tunneling of programming and erase functions which are performed through a thin tunnel oxide layer 6 of less than 100 .ANG. in thickness, which is not thick enough to provide for adequate reliability and production yield.
In addition, the bitline resistance is high because of the small cross sectional area of the bitlines in high density memory devices which necessarily limit the size of elements of the device.
U.S. Pat. No. 5,262,846 of Gill et al for "Contact-Free Floating-Gate Memory Array with Silicided Buried Bitlines and with Single-Step-Defined Floating Gates" shows a prior art process for forming a buried bitline EEPROM.